Implementation of Otsu's thresholding process based on FPGA

Abstract

Otsu's global automatic image thresholding method has been widely employed in various real-time applications. In this paper, an implementation on FPGA (Field Programmable Gate Array) using Altera's Cyclone II series chip for the BCVC (Between Class Variance Computation) of Otsu's method is presented to meet these high speed requirements. The hardware implementation takes advantage of parallel computation capabilities offered by FPGA technology. The proposed architecture employs Altera's megacore to eliminate the complex divisions and multiplications in the Otsu's procedure. The FPGA implementation architecture is verified on DE2 board to enable real-time image segmentation, and the experimental results indicate that the system can obtain a good performance of image segmentation.