Implementation of Multi-bin CABAC Decoder in HEVC/H.265 on FPGA

Abstract

Context-based adaptive binary arithmetic coding (CABAC) is specified as the single operation mode for entropy coding in the newest standard High Efficiency Video Coding (HEVC). While it provides high coding efficiency, the data dependencies in H.265/HEVC CABAC make it challenging to parallelize and thus, limit its throughput. This paper proposes a multi-bins CABAC decoder architecture adaptive to HEVC syntax elements with small FSM (finite state machine) for the control of SE order. In order to reduce the critical path delay, we exploit different techniques of optimization such as a speculative decoding, logic balancing techniques and our proposed technique RLpsLZpStateIdx LUT. The parallel implementation can process 1,34 bin/cycle when operate at 134,23 MHz and improved high throughput of 179.86 Mbin/s with an optimized path delay compared to the serial process. The architecture is coded using VHDL ISE language, simulated and synthesized using Xilinx tools with virtex4 xc4vsx25-12ff668 board.