Implementation of Low Power Scalable Encryption Algorithm

Abstract

SEA – Scalable Encryption Algorithm is a block cipher based symmetric encryption scheme, particularly intended for resource constrained devices. SEA proposes low computational cipher schemes, that is, miniaturized code size, memory and power, developed for processors with a restricted instruction set. SEA is parametric with plain-text, key and microprocessor size, and found to be powerful with the grouping of encipherment or decipherment and derivation of the keys. SEA was primarily meant for software implementations in microcontrollers, smart cards and small embedded systems. In this article, we look into the performance investigation of modified SEA with efficient modular adder in a Field programmable gate array (FPGA) device. For this reason, a loop based iterative design of the block cipher is realized on FPGA. Apart from its minimum cost, the proposed modified design is entirely flexible with any parameters and acquires advantage of generic VHDL coding. The efficient modular adders implementation based modification in SEA achieves lower area, power consumption and considerably higher throughputs on the target platform VIRTEX-4, xc4vl25 and SPARTAN-3, xc3s1400.