Implementation of Interval Arithmetic Algorithms on FPGAs

Abstract

Interval arithmetic provides an efficient method for monitoring and controlling errors in numerical calculations and can be used to solve problems that cannot be efficiently solved with floating-point arithmetic. However, existing software packages for interval arithmetic are often too slow for numerically intensive calculations. While conventional floating point arithmetic is provided by fast hardware, interval arithmetic is simulated with software routines based on integer arithmetic. Therefore, the hardware design for interval arithmetic can provide a significant performance improvement over software implementations of interval arithmetic. In this paper, we design and implement interval arithmetic algorithms. The proposed method performs interval intersection, hull, minimum, maximum, and comparisons, as well as floating-point minimum, maximum and comparisons. Compared to the corresponding Forte Fortran 95 interval operations, about 80% reduction in the number of instructions is obtained with the proposed method. In short, it is found to greatly speedup the interval operations of hull, intersection, maximum, minimum, and comparisons over the corresponding Forte Fortran 95 interval operations.