Implementation of IEEE 754 compliant single precision floating-point adder unit supporting denormal inputs on Xilinx FPGA

Abstract

FPGA based reconfigurable computing accelerators are increasingly being used in high performance and scientific computing applications to achieve higher performance. These applications demand high numerical stability and accuracy and hence usually use floating-point arithmetic. The floatingpoint arithmetic cores available from major FPGA vendors are not fully IEEE 754 compliant. These cores do not support denormal numbers. In this paper we describe our implementation of IEEE 754 compliant single precision floatingpoint adder that supports denormal inputs. Further, we compare its performance and resource utilization against the Xilinx floating-point adder IP core. Our implementation has eight stages of pipeline, utilizing minimal FPGA resources; it can operate at frequencies greater than 300 MHz.