Implementation of high-resolution reticle inspection in wafer fabs

Abstract

Many advanced wafer fabs are currently fabricating devices with 130nm or smaller design rules. To meet the challenges at these sub-wavelength technology nodes, fabs are using a variety of resolution enhancement techniques (RETs) in lithography and exploring new methods of processing, inspecting and requalifying photomasks. The acceleration of the lithography roadmap imposes more stringent requirements on mask qualification and requalification to ensure that device yields are not compromised: mask inspection tools of today need to find smaller defects on reticles against considerably more complicated patterns or tighter critical dimensions (CDs). In this paper we describe the early stages of implementation and proliferation of advanced reticle inspection tools at high volume manufacturing wafer fabs. The fabs run incoming multi-surface contamination inspections on masks sent from the mask shop (Intel Mask Operations, IMO), and follow them up with periodic inspections/review to make sure any new contaminant or damage does not go undetected. When necessary, images of defects are electronically presented to engineers at IMO for review. Reticle requalification with these inspection tools reduces or eliminates the need for print test verification. We describe the tools and procedure used to streamline reticle requalification at the fabs and improve the feedback loop between the fabs and the mask shop.