Implementation of high-peed multi-level QAM modems based on Xilinx Virtex-II FPGA

Abstract

This paper describes an implementation of high-speed multi-level quadrature amplitude modulation (QAM) modems using Xilinx Virtex-II field programmable gate arrays (FPGA). The design starts with system-level simulations and exploits different architectures and algorithms available for digital filters, which is a key component of a QAM modem. System efficiency is highlighted with the parallel-pipelined structure and look-up table based implementation, such that the design benefits from performance as well as chip size. Sufficient arithmetic precision is employed in the internal data-path to avoid the possibility of overflow so that the digital filter always presents a full-precision result at its output; thus precision need not be sacrificed to attain high-speed. The benchmarks indicate that the maximum input bit rate can reach 330 Mbps for 64-QAM.