Implementation of High Speed Area Efficient Variable Latency Adder

Abstract

The adders are basic building blocks of the digital circuits for the Signal processing, Integrating and other process of operation. There are various types of adders are proposed in Literature which are commonly used in VLSI Design. The Ultimate aim of the VLSI Design is to reduce the number of gates, power, Delay and they are the Important factors which are taken in consideration. In this Paper a comparative analysis of Speed, Power consumption, Area and Power delay Product (PDP) are implemented for design of Carry Skip Adder with other adders as Ripple Carry Adder and Parallel Prefix Adders. The Simulation results also shows that the proposed adder is Faster and Area efficient compared to other adders. They estimates the performance of proposed design will be better in terms of Logic and route delay by experimental results.