Abstract
We describe UbiNetics implementation of turbo decoders for 3/sup rd/ generation mobile communications. A turbo encoder has been agreed as the channel coding technique for high rate traffic channels by the 3(/sup r/d) Generation Partnership Project (3GPP); a group of international manufacturers and operators working towards a world-wide standard for 3G mobile communications. At UbiNetics we decode these channels on fixed point DSPs. Presently a single 200 MHz Texas Instruments DSP from the C62x family can decode, with 4 iterations, traffic channels at rates beyond 200 kbits/s. This is achieved using processor non-specific software written in C. With optimisation of critical sub-functions in assembly language we estimate that it should be possible to decode channels at around 400 kbits/s on a single 200 MHz processor. We describe the issues involved in the fixed-point implementation of a turbo decoder. We discuss the design choices that need to be made regarding the form of the decoder, and justify with floating point simulation results the choices we made. We then describe issues involved in implementing a turbo decoder on a fixed-point processor with a limited amount of memory, and give details of the solutions we used. Comparisons of results from our workstation based floating point simulations and those achieved on the fixed-point target platform are presented. The performance of the two is shown to be virtually identical.
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