Implementation of Hardware Efficient Chaotic Generators for Signal Security in Portable Systems

Abstract

In this paper, implementation of chaotic sequence generators on Field Programmable Gate Array (FPGA) devices are presented. The chaotic sequence generators designed here are based on two different chaotic map functions The Logistic Map and the Tent Map functions. Many properties of these chaotic sequences are similar to pseudorandom sequences (pn-sequences), used for cryptography and hence it can also be used for encrypting the signals and data, for security purposes. A novel representation of floating-point number and a balanced architecture for hardware design have facilitated in reduction of hardware and power consumption. The chaotic generator designed here, consume less power and have better speed and the hardware usage is less than similar work. Maximum frequency of operation for the system designed in this work are 35.442 MHz and 26.134MHz for Tent map based and Logistic map based system respectively The randomness of the sequence generated by the chaotic generators is analyzed.by NIST test suit, to test for its randomness.