Implementation of folding transformations on linear VLSI processor arrays

Abstract

Folding transformations on processor arrays result in smaller processor arrays, more efficient work for the processing elements, a decrease in I/O time, pipelineable implementations, circular data flow, as presented in [1], Some implementations of folding transformations are considered by Megson and Evans in [2], Choffrut and Culik in [3], Yaacoby and Cappello [4] and by the authors in [1,5,6]. A case study and generalised procedure for folding transformation is given here. The generalised procedure is realised to keep the complexity of the data communications, the processor operations, the regular data flow and avoid data collision. Multi-dimensional processor arrays are considered and some examples of linear processor arrays are given. The most common types of the algorithms are presented, determining all the possible planes (lines) of symmetry and vectors of the interlocking translation. Few theorems are available to determine which of the offered folding transformations are the best. The triangular system solver is presented to demonstrate the proposed procedure of implementation. All the implementations obtained are given in the Appendix. The efficiency analysis shows that the implementation obtained utilizes the processor array with double efficiency. Moreover by using the same processor array problems with double dimension can be solved. Also the circular data flow can be used for cascaded algorithms.