Implementation of Efficient Parallel Prefix Adders for Residue Number System

Abstract

In this paper we proposed a high speed and area efficient Kogge-stone, Ladner-fischer and Knowles adders by modifying the existing architectures by eliminating the redundant black cells. Currently the speed of the multipliers are restricted by the speed of adders for partial products addition. The major problem with the binary addition is the carry chain delay, to address this problem most of the modern adder architectures are implemented using parallel prefix adders. The delay of the parallel prefix adders are directly proportional to the number of levels in the carry propagation stage. Due to the logarithmic delay of the parallel prefix adders delay problems have effectively reduced. Kogge-stone is one of the fastest adders. We has eliminated the redundant black cells and performed re-routing thus minimizing the logic delay compared to the previous adders. Coded modified architecture in Verilog HDL, Simulated and synthesized using Xilinx ISE. Compared the modified architectures of Kogge-stone, Ladner-fischer & Knowles adders are found to be an improvement in the delay with the previous adders.