Implementation of Digital Pulse Width Modulators Using Frequency Divider Method in FPGA

Abstract

The Digital pulse width modulators are used for digital control applications. When the requirement of clock frequency exceeds the required limit the switching frequency of the power converter also increased. In this paper a new architecture for digital pulse width modulator is proposed. The proposed method is based on digital clock manager which is present in the Spartan 3 FPGA. The architecture will be implemented in FPGA Spartan 3 and the performances are verified.