Abstract
A digital HDTV video decoder system is designed and implemented by using multiple multimedia video processors in a loosely-coupled multi-processor architecture. This decoder system can decompress video bitstream up to 20 Mbits/s and produce analog output at HDTV pixel rate. This design has the advantage of hardware scalability to adapt different picture resolutions and computation requirements. The design target is the video subsystem of a digital HDTV receiver.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
