Abstract

The wireless local loop (WLL) system has been deployed as a new application for wireless communication with fixed subscriber units which impose a fixed propagation and no handoffs compared to the wireless mobile communication systems. The design of the WLL system is much simpler than that of a mobile system because no handoff occurs in a fixed-to-fixed link. This paper describes hardware design and the implementation of the code acquisition module and code tracking loop module of the base station receiver for the code division multiple access (CDMA) WLL system proposed by the Electronics and Telecommunications Research Institute (ETRI). These modules of the CDMA WLL system are implemented by hardware chips, such as digital signal processors (DSP), erasable programmable logic devices (EPLD), and field programmable gate arrays (FPGA). Timing simulation of the implemented system is operated using the ALTERA MAXPLUS tool. The basic hardware modules of the base station receiver consist of two searchers for antenna diversity and four fingers for multi-path combining. We verify the operation of the code acquisition and time tracking loop on the call test. The reconstructed voice data show good quality in the reverse link. It will be possible to implement an ASIC design in the use of this code acquisition and code tracking loop module.

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