Abstract
The Binarized Neural Network (BNN) is a Convolutional Neural Network (CNN) consisting of binary weights and activation rather than real-value weights. Smaller models are used, allowing for inference effectively on mobile or embedded devices with limited power and computing capabilities. Nevertheless, binarization results in lower-entropy feature maps and gradient vanishing, which leads to a loss in accuracy compared to real-value networks. Previous research has addressed these issues with various approaches. However, those approaches significantly increase the algorithm’s time and space complexity, which puts a heavy burden on those embedded devices. Therefore, a novel approach for BNN implementation on embedded systems with multi-scale BNN topology is proposed in this paper, from two optimization perspectives: hardware structure and BNN topology, that retains more low-level features throughout the feed-forward process with few operations. Experiments on the CIFAR-10 dataset indicate that the proposed method outperforms a number of current BNN designs in terms of efficiency and accuracy. Additionally, the proposed BNN was implemented on the All Programmable System on Chip (APSoC) with 4.4 W power consumption using the hardware accelerator.
Highlights
The Binarized Neural Network (BNN) refers to the Convolutional Neural Network (CNN) which are made up of only bipolar data for weights and activation
There are some limits to measuring the efficiency of our topology since BNNs performance will fluctuate with many factors, such as data enhancement, approaches of the optimizer, and so on
BNN topology comparison is limited to its scenario and does not reveal the full potential of this type of BNN structure
Summary
The Binarized Neural Network (BNN) refers to the Convolutional Neural Network (CNN) which are made up of only bipolar data for weights and activation. The accuracy of BNN model has always been substantially inferior to a real-value model with the same topology due to the limited information entropy. Recent studies such as MeliusNet [2], IRNet [3], and ReactNet [4] have worked hard to bring BNN’ Top-1 on ImageNet dataset to more than 0.70, which is 3% lower than the corresponding real-value models with amounts of arithmetic operations. The objective is to develop a highly effective BNN application with endeavours in network topologies and customized hardware architecture. A novel BNN topology was proposed and its FPGA-based acceleration cores, which were deployed on the APSoC device. It is well suited to programmable hardware due to its simple and regular architecture
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