Implementation of an instruction dispatch unit applied to digital signal processors with VLIW architecture

Abstract

Digital signal processor (DSP) is a particular kind of processor that is able to achieve a variety of digital signal processing algorithms rapidly. Nowadays, the hardware of the DSP of the high performance relies on the Very Long Instruction Words (VLIW) architecture, which takes advantage of instruction level parallelism and executes instructions in parallel to accomplish computing-intensive tasks. However, VLIW machines are strict not only in instruction dispatching but also with the control of the branch. It is essential to ensure the correct executions of the programs in every pipeline stage. In this paper, an instruction dispatch unit is proposed, which serves to VLIW processors. It is modeled and detailed described in Verilog HDL, emulated by VCS tools and synthesized by Design Compiler in 0.13 µm CMOS technology. The final result indicates that the dispatch unit works well at the clock rate of 400 MHz, as the critical path delay of the proposed design is 2.3 ns.