Implementation of an imprint damascene process for interconnect fabrication

Abstract

Advanced integrated circuits require eight or more levels of wiring to transmit electrical signal and power among devices and to external circuitry. Each wiring level connects to the levels above and below it through via layers. The dual damascene approach to fabricating these interconnected structures creates a wiring level and a via level simultaneously, thereby reducing the total number of processing steps. However, the dual damascene strategy (of which there are several variations) still requires around 20 process steps per wiring layer. In this work, an approach to damascene processing that is based on step-and-flash imprint lithography (SFIL) is discussed. This imprint damascene process requires fewer than half as many steps as the standard photolithographic dual damascene approach. Through use of a template with two tiers of patterning, a single imprint lithography step can replace two photolithography steps. Further improvements in efficiency are possible if the imprint material is itself a functional dielectric material. This work is a demonstration of the compatibility of imprint lithography (specifically SFIL) with back-end-of-line processing using a dual damascene approach with functional materials.