Implementation of an efficient FPGA architecture for capsule endoscopy processor core using hyper analytic wavelet-based image compression technique

Abstract

To receive images of human intestine for medical diagnostics, wireless capsule endoscopy (WCE) is a state-of-the-art technology. This paper proposes implementation of efficient FPGA architecture for capsule endoscopy processor core. The main part of this processor is image compression, for which we proposed an algorithm called as hyper analytic wavelet transform (HWT). The hyper analytic wavelet transform (HWT) is quasi shift-invariant; it has a good directional selectivity and a reduced degree of redundancy. Huffman coding also used to reduce the amount of bits required to represent a string of symbols. This paper also provided forward error correction (FEC) scheme based on low density parity check codes (LDPC) to reduce bit error rate (BER) of the transmitted data. Compared to the similar existing works this paper proposed an efficient architecture.