Implementation of a test wafer inventory tracking system to increase efficiency in monitor wafer usage

Abstract

The process of building integrated circuits requires that semiconductor manufacturers spend millions of dollars annually on the purchase of test wafers. These test wafers are used to qualify tools, monitor processes, and develop new process techniques. Reducing the number of test wafers brought into the manufacturing process is critical to overall cost containment and improved efficiency. Other considerations for reducing the number of test wafers include the amount of time spent tracking down misplaced material, the potential for contamination and tool downtime if the wrong used test wafers are processed in the wrong tool, lost manufacturing capacity due to excessive storage of test material, and downtime resulting from a lack of test wafers due to poor test wafer management. In an effort to reduce costs spent on test wafers, many companies use reclaim to polish off the top surface of the test wafer. This provides a clean wafer suitable for re-use at a much reduced cost. In many cases, however, wafers are sent out for reclaim before their full internal re-use potential is realized, offsetting some of the cost savings. This is most likely due to the complexity in identifying downgrading paths and controlling the inventory of generated used test wafers. Motorola MOS12 recognized a need for a system that would significantly reduce the amount of money spent on test wafers by optimizing internal re-use opportunities implementation of this system required manufacturing and engineering to work together to determine which flows could be safely re-used and where, without negative impact to manufacturing. A matrix was constructed identifying all potential re-use opportunities. This system automates the test wafer ordering process, and forces used material to be used whenever possible, maximizing test wafer re-use. This paper win outline the necessary requirements for the development and installation of an efficient, automatic test wafer management system.