Abstract

Forward error correction (FEC) plays a vital role in digital communication systems. DVB-T system uses FEC as a channel coding technique to restore any data lost through transmission to the receiver. DVB-T system uses two levels of error protection. The first level is applied in the data transmitted by using a Reed-Solomon RS (204, 188) code followed by a convolutional interleaver. The other level of error protection is a punctured convolutional inner coding followed by an inner interleave in which the data sequence is rearranged again to minimize the influence of burst errors.This paper describes the implementation of inner convolutional codec (Convolutional coder and Viterbi Decoder) and inner de/interleaving of a standard DVB-T system with a constrained length of 7 and a code rate of 2/3 using VHDL on virtex-6 FPGA xc6vlx240t. The designed channel convolutional encoder and Viterbi decoder follow European Standard ETSI EN 300 744 for digital terrestrial television. Verification of the design is accomplished by loop back and by comparison with the corresponding Xilinx core. Utilization and timing re-ports of the implemented device on Vertex 6 are included.

Highlights

  • Digital video broadcasting terrestrial (DVB-T) is the name of the terrestrial transmission system developed by the DVB Project

  • This paper describes the implementation of inner convolutional codec (Convolutional coder and Viterbi Decoder) and inner de/interleaving of a standard DVB-T system with a constrained length of 7 and a code rate of 2/3 using VHDL on virtex-6 field programmable gate array (FPGA) xc6vlx240t

  • It consists of the model for the convolutional encoder, the after encoder block that acts as a parallel to serial block, the full system block that consists of inner interleaver and inner deinterleaver),the pre-decoder block that acts as serial to parallel block,and the viterbi decoder

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Summary

Introduction

Digital video broadcasting terrestrial (DVB-T) is the name of the terrestrial transmission system developed by the DVB Project. [4] This algorithm uses trellis structure, which is traced back for decoding the received information.[4] it performs maximum likely hood detection on data that is coded by the convolutional encoder.[4] Viterbi decoding uses trellis diagram to get the output data that is most likely similar to the input sequence coming from the encoder. It reduces the complexity by using trellis structure.

Inner coding of DVB-T system model
DVB-T transmitter
Puncturing
Punctured internal encoder
Symbol interleaver
Inner deinterleaver
Inner interleaver
Bit-wise interleaver
Viterbi decoder
VHDL modeling and simulation results
Convolutional encoder and soft viterbi decoder waveforms
Inner interleaver and inner deinterleaver waveforms
Proposed soft viterbi decoder vs Xilinx IPcore soft viterbi decoder waveforms
Logic design summary
Timing summary
Conclusion
Full Text
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