Abstract
A single-chip VLSI implementation of a 4 by 4 prioritized router for multistage real-time interconnection networks is presented. The chip employs packet switching and facilitates 32-bit priority arbitration by means of a priority forwarding scheme that prevents priority inversion and which provides accurate priority control in a network. The packets are of fixed size, having three 38-bit segments: a header and two bodies. Each input port has an 8-packet priority queue for simultaneous input and output, enabling virtual cut-through routing. The chip is pipelined with a 25-ns pitch and reduces the number of stages to two by overlapping the arbitration and priority queue stages. Hence, its data transmission rate is 190 MByte/s per port. The end-to-end delay of an s-stage network is 25/spl times/(2s+1) ns. >
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.