Abstract

Journal of Electronics ManufacturingVol. 03, No. 03, pp. 121-131 (1993) PAPERSNo AccessImplementation of a decision support system for scheduling semiconductor test operationsCHUNG-YEE LEE, LOUIS A. MARTIN-VEGA, REHA UZSOY and JIM HINCHMANCHUNG-YEE LEEDepartment of Industrial and Systems Engineering, University of Florida, Gainesville, FL 32611, USA Search for more papers by this author , LOUIS A. MARTIN-VEGACollege of Engineering, Florida Institute of Technology, Melbourne, FL 32901-6988, USA Search for more papers by this author , REHA UZSOYSchool of Industrial Engineering, 1287 Grissom Hall, Purdue University, West Lafayette, IN 47907-1287, USA Search for more papers by this author and JIM HINCHMANHarris Semiconductor Corporation, Melbourne, FL 32902, USA Search for more papers by this author https://doi.org/10.1142/S0960313193000140Cited by:22 PreviousNext AboutSectionsPDF/EPUB ToolsAdd to favoritesDownload CitationsTrack CitationsRecommend to Library ShareShare onFacebookTwitterLinked InRedditEmail AbstractThe problem of scheduling semiconductor test operations is a dynamic job shop scheduling problem complicated by the presence of machines with different scheduling characteristics and sequence-dependent setup times. The well-known intractability of job shop scheduling problems and the need to address multiple, conflicting management goals motivates the use of a decision support system (DSS) combining scheduling heuristics and existing information systems to support the scheduling function. The DSS is currently in use in two separate testing facilities, where management feels it has significantly improved shop performance and reduced production planning workload.Keywords:Semiconductor testingschedulingdecision support systems FiguresReferencesRelatedDetailsCited By 22Modeling and Solving Scheduling Problems in PracticeMichael L. Pinedo11 February 2016Optimal test capacity allocation in automated high-frequency testing environmentsYong-Hee Han and Sung-Seok Ko2 December 2011 | The International Journal of Advanced Manufacturing Technology, Vol. 62, No. 1-4Constructing a production exception handling system for the semiconductor manufacturing processTsu‐Ming Yeh18 Oct 2011 | Kybernetes, Vol. 40, No. 9/10A two-phase dynamic dispatching approach to semiconductor wafer testingYin-Yann Chen, James T. Lin and Tzu-Li Chen1 Oct 2011 | Robotics and Computer-Integrated Manufacturing, Vol. 27, No. 5Product–process interface for manufacturing data management as a support for DFM and virtual manufacturingJawhar Elgueder, Florent Cochennec, Lionel Roucoules and Emmanuelle Rouhaud23 October 2010 | International Journal on Interactive Design and Manufacturing (IJIDeM), Vol. 4, No. 4Scheduling semiconductor final testing a DBR based simulation modelWu-Der Jeng and Meng-Shiun Tsai1 Jul 2010The Construction of a Real-Time WIP Exception Monitoring System for Semiconductor IndustryTsu-Ming Yeh, Fan-Yun Pai and Ching-Shih Tsou1 Oct 2008Improved customer satisfaction with a hybrid dispatching rule in semiconductor back-end factoriesDavid M. Chiang, Ruey-Shan Guo and Fan-Yun Pai1 Sep 2008 | International Journal of Production Research, Vol. 46, No. 17Design and manufacturing interface modelling for manufacturing processes selection and knowledge synthesis in designAchraf Skander, Lionel Roucoules and Jean Sébastien Klein Meyer21 June 2007 | The International Journal of Advanced Manufacturing Technology, Vol. 37, No. 5-6Solution strategies for multi-stage wafer probing scheduling problem with reentryW L Pearn, S H Chung, M H Yang and K P Shiao21 December 2017 | Journal of the Operational Research Society, Vol. 59, No. 5In-house development of scheduling decision support systems: case study for scheduling semiconductor device test operationsT. Freed, K. H. Doerr and T. Chang26 September 2007 | International Journal of Production Research, Vol. 45, No. 21A WIP-based exception-management model for integrated circuit back-end production processesRuey-Shan Guo, David M. Chiang and Fan-Yun Pai6 May 2006 | The International Journal of Advanced Manufacturing Technology, Vol. 33, No. 11-12Multi-objectives exception management model for semiconductor back-end environment under turnkey serviceR.-S. Guo, D. M. Chiang and F.-Y. Pai22 March 2007 | Production Planning & Control, Vol. 18, No. 3A parameterized-dispatching rule for a Logic IC sort in a wafer fabricationJ. T. Lin, F. K. Wang * and P. C. Kuo21 February 2007 | Production Planning & Control, Vol. 16, No. 5PRACTICE-FOCUSED RESEARCH ISSUES FOR SCHEDULING SYSTEMS*KENNETH MCKAY, MICHAEL PINEDO and SCOTT WEBSTER5 January 2009 | Production and Operations Management, Vol. 11, No. 2Scheduling semiconductor device test operations on multihead testersT. Freed and R.C. Leachman1 Nov 1999 | IEEE Transactions on Semiconductor Manufacturing, Vol. 12, No. 4A framework for decision support systems for scheduling problemsKlaus Ecker, Jatinder N.D. Gupta and Günter Schmidt1 Sep 1997 | European Journal of Operational Research, Vol. 101, No. 3A Generic Decomposition Procedure for Semiconductor Testing FacilitiesIrfan M. Ovacik and Reha Uzsoy1 Jan 1997An iterative heuristic for the single machine dynamic total completion time scheduling problemSuresh Chand, Rodney Traub and Reha Uzsoy1 Jul 1996 | Computers & Operations Research, Vol. 23, No. 7GLOBAL JOB SHOP SCHEDULING WITH A GENETIC ALGORITHMJEFFREY W. HERRMANN, CHUNG-YEE LEE and JIM HINCHMAN5 January 2009 | Production and Operations Management, Vol. 4, No. 1A REVIEW OF PRODUCTION PLANNING AND SCHEDULING MODELS IN THE SEMICONDUCTOR INDUSTRY PART II: SHOP-FLOOR CONTROLREHA UZSOY, CHUNG-YEE LEE and LOUIS A. MARTIN-VEGA1 Sep 1994 | IIE Transactions, Vol. 26, No. 5Decomposition algorithms for scheduling semiconductor testing facilitiesE. Demirkol, R. Uzsoy and I.M. Ovacik Recommended Vol. 03, No. 03 Metrics History Received 1 June 1993 Accepted 1 July 1993 KeywordsSemiconductor testingschedulingdecision support systemsPDF download

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