Implementation of a context-addressed pipeline 3 SIMD architecture

Abstract

The context-addressed SIMD architecture is being examined as a means to provide suitable processing capabilities for non-numeric applications. This paper considers techniques which are being applied to realize this architecture in a segment sequential fashion.A fixed head disc provides a large amount of sequential storage already segmented into tracks. Economical bit-serial microprocessors are employed one per track to process the instructions and data sequentially as the disc rotates. A microprocessor and its track are here called a cell. A chain of cells can search a file consisting of fixed length words organized into variable length records in one revolution or cycle of the disc. Intercell communication in the chain as a pipeline allows files and records which overlap segment boundaries to be processed as an intact file or record, with all segments processed in parallel. Transfers of words and bits in pipeline fashion between cells allows the file to change size dynamically without regard for its cellular segmentation, as words may be either inserted or deleted within a record.Instruction execution in this architecture is also pipelined. The next instruction is preprocessed in one cycle along with its operand while the current instruction is executing, and the previous one is finishing up its operation or post-processing. This instruction pipelining is performed in order to minimize the execution time for a sequential instruction by overlapping the instruction fetch and execute of two consecutive cycles. The segment sequential organization also demands that the instruction execution continue into the next cycle in order to process the elements of a record that may overlap segments. Again by overlapping this instruction clean-up with the next instruction's execution, we may minimize the instruction execution time.A hardware realization of this pipeline of cells which pipelines its instruction execution becomes another pipeline. Each bit serial microprocessor is in fact a pipeline of modules each performing some phase of instruction execution or segment support such as garbage word deletion or new data insertion. The segment sequential architecture lends itself very nicely to this pipeline 3 approach.Although they provide a powerful architecture, these three pipeline constructs also develope new problems in their control and timing. Such problems include that the words which are pipelined between cells are not processed twice, missed entirely, or only partially processed by the instruction pipeline. A solution to these and to other problems related to this architecture are presented in this paper.