Implementation of a closed loop SHMPWM technique for three level converters

Abstract

High power converters are built using high-voltage and high-current rated semiconductors. The commutation of these devices imply large amounts of energy per cycle leading to very low switching frequency in order to avoid a high rise on the semiconductors temperature. The consequence is high harmonic distortion generated by the converter. Grid codes requirements specify the maximum admitted harmonic distortion. The well known selective harmonic elimination pulse width modulation (SHEPWM) technique has proved to be useful in eliminating some of the undesired harmonics without increasing the switching frequency, leaving the rest of them free. The solution to the rest of harmonics is to add bulky and expensive filters. Recently, the method named selective harmonic mitigation pulse width modulation (SHMPWM) has been introduced. The aim of this technique is to mitigate the amplitude of the undesirable harmonics, to acceptable values to meet the grid code, considering a larger number of harmonics. In this paper a practical implementation of this technique in a closed loop scheme is presented. The experimental results using a 150 kW three-level diode-champed converter show that the output signals meet the EN 50160 and CIGRE WG 36-05 grid codes. Comparisons between SHMPWM and SHEPWM are included in the experiments, showing the superior performances of the SHMPWM technique.