Implementation of a binary translation for improving ECU performance

Abstract

An energy-area efficient IVN-connected software execu tion architecture in ECU processor is proposed. ECU processor is commonly implemented using the conventional embedded process or only providing the fixed services, which includes statically com piled embedded software in on-chip flash memory. Instead of con ventional on–chip flash memory for an instruction code area, we a dopt a virtually mapped internal memory concept to realize IVN- connected software execution, in where the storage area of VCU i s indirectly mapped onto the physical address space of the instruc tion memory using a binary translation. The proposed IVN-conne cted architecture of the system enables on-demand code execution for the instructions, which are fetched from the IVN-side storage area of VCU in the runtime, instead of using a directly-connected on-chip instruction bus. The proposed storage-less approach may be adopted to reduce the high access current and large chip area o verhead by in order to retrieve the requested instruction, a small- sized RAM scratch pad is adopted for retaining the hot-spot instr uction code and early filled with pre-estimated instruction sector. As the result of this paper, we show that the proposed technique r educes the energy consumption and packet delay of ECU for exec uting the embedded software, as well as the reduced chip area by realizing a storage-less ECU architecture.