Abstract
Multipliers are used in the building blocks of several processors. Conventional multiplication is time consuming and lengthy process; to overcome these drawbacks the circuit designers must develop speedy multipliers. Vedic multipliers can be utilized for high speed multiplication process. In Designing of CMOS circuits an issue of area is always there, to reduce this Gate Diffusion input (GDI) technique can be used. The GDI concept assist in reduction of Transistor Count (TC), due to this power dissipation is minimized. In this study the design of fast speed 4×4 Vedic Multiplier has been presented using GDI technique. The power dissipation of proposed multiplier is reduced as compared to conventional CMOS multiplier.
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