Implementation of 3D graphics accelerator using full pipeline scheme on FPGA

Abstract

This paper proposes effective 3D graphics hardware. It is designed to support the OpenGL ES 2.0 and Shader model 3.0. We develop all module (vertex shader, clipping engine, triangle setup engine, rasterizer, pixel shader and raster operator) of 3D pipeline on FPGA using RTL design. The proposed hardware of which total gate count is about 1.486M operates with 100Mpixels/sec at pixel shader. Compared to the other product of a company, the proposed architecture result in about 50% improvement in term of cycle.