Implementation of 144 × 64 Pixel Array Bezel-Less Cmos Fingerprint Sensor

Abstract

Abstract This paper proposes CMOS integrated 144 × 64 pixel array fingerprint sensor without a bezel electrode. In this paper, the architecture of CMOS capacitive fingerprint sensor readout circuit is presented for general type of a switched capacitive integrator scheme. The pipelined scan driver is included in the fingerprint sensor for fast image capture. It is implemented on 0.35 μm standard CMOS process technology. The operation is validated by SPECTRE for one-pixel and RTL simulation including logic synthesis for a full chip design on condition of 0.35 µm typical CMOS process and 3.3 V power. The layout is performed by full custom flow for sensor cell array and auto P&R for a full chip. The area of a full chip is 4943 μm × 3943 μm and the gate count is 542,000. The area of one-pixel is 48 × 48 µm2. The pitch is 50 µm and image resolution is 508 dpi and power consumption is less than 3 mA.