Implementation Aspects of Multi-bit Adders Using UTBSOI Transistors

Abstract

This paper presents implementation aspects of popular multi-bit adders (e.g. ripple carry adder (RCA) and carry look ahead adder (CLA)) through UTBSOI transistors. Performance parameters comparison in terms of power consumption, delay, power-delay product (PDP), and energy-delay product (EDP) have been analysed for the application of the intelligent systems. The 4-bit adders are simulated at 45-nn regime in Cadence-spectre using the BSIM-IMG model for the UTBSOI technology. From the simulation results, it is observed that the power consumption in UTBSOI-based RCA (UTB-RCA) is four times lesser than that of in UTBSOI-based CLA (UTB-CLA). The delay exhibited by the UTB-RCA and UTB-CLA at 20 MHz operating frequency is 0.1085 ns and 0.3151, respectively. Based on the simulation results, the application of UTBSOI in the RCA has resulted in 84.3% and 3.67 times improvements over that of existing design architecture in the literature in terms of power consumption and delay, whereas the use of UTBSOI in CLA does not seem to enhance the power consumption and delay over the conventional designs.