Implementation architecture of a variable forward error correction decoder

Abstract

As the demand for wireless transmission of multimedia data increases, simple application of a single FEC code is not adequate to meet the unique requirements of multiple data types, as these data types often have highly variable error tolerances. Variable forward error correction (VFEC) is a technique of applying a family of FEC codes with a wide range of coding rates to provide unequal error protection. In this implementation, we achieve VFEC by adopting the family of 63-bit binary BCH codes which are generated by the finite field GF(2/sup 6/). Since the primary implementation challenge of an error correction system is often concentrated on the decoder design, this paper is devoted to defining a VFEC decoder architecture. By exploiting the redundancies between these codes, we observe that a majority of the decoder hardware can be reused among codes, resulting in an implementation that is only slightly more complicated than a single FEC decoder. In this paper, an architecture and the control logic for a single binary BCH decoder is presented, which can then be extended to a VFEC decoder design.