Implementation and Verification of Steganography IP Core Based on HLS and OpenCV

Abstract

Steganography is a safe transmission method that hides secret data in public information to avoid attacks as much as possible. However, the current steganography research and application mainly stay in the software stage. Although the secure transmission of data is realized, it is difficult to realize the purpose of high-speed data transmission. This thesis solves this problem with the help of a fully parallel, high-speed and high-bandwidth FPGA. This paper uses HLS to design a steganography IP core that can be applied to FPGA, and uses OpenCV to quickly and effectively verify the IP core. The final result proves that this paper successfully designed a high-performance IP core that can realize steganography, which effectively solves the problem of difficult high-speed transmission of encrypted data. This IP core combines the AXI bus protocol, which not only facilitates data interaction with DDR3 and other devices, but also conducive to the design and optimization of the complete secret data transmission system in the future.