Implementation and Verification of IEEE-754 64-bit Floating-Point Arithmetic Library for 8-bit Soft-Core Processors

Abstract

Dedicated 64-bit Floating-Point (FP) hardware is usually not feasible in space-constraint or low-cost FPGA systems. Such systems may, however, need FP operation from time to time. This paper addresses the problem by implementing a fully compatible 64-bit IEEE-754 FP library for 8-bit PicoBlaze processor, which is synthesizable on almost all XILINX FPGAs. This reduces the resource required dramatically. For example, the number of Lookup Tables (LUT) required by an FP IP Core is 31,131; whilst the soft-core processor consumes only 123 LUTs, a 250-fold decrease. A 64-bit FP division operation using the proposed library takes an average clock count of 6,850 cycles. A test bench is setup to perform code verification using comparison method to ensure exactness of results with an ARM-based hardcore FP unit. Verification mechanism is based on Inter-Processor Communication (IPC), shared memory, and interrupt signalling which they are all implemented on an all programmable System- on-Chip XILINX Zynq Ultrascale+ FPGA platform.