Abstract
Low-Voltage Differential Signaling (LVDS) evolves over the last decade to meet specific requirements such as Bus LVDS and Multipoint LVDS. This paper first presents a method to implement the multi-channel LVDS in the parallel RapidIO protocol using CPLD device and VHDL language, followed by a detailed discussion of the data line transmission error generated during the process of high-speed data transportation due to clock-data skew and difference between transmission lines. A logical component, 4-bit-channel aligner, is developed and simulated to solve this sort of transmission error. Finally, an evaluation board of RapidIO protocol is developed to evaluate the correctness of multi-channel LVDS data transmission. Some experiments show that the multi-channel LVDS is simple and strong anti-interference.
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