Implementation and Research of Multi Pre-fetch Mechanism Fusion Technology in Memory Subsystem

Abstract

The “memory wall” acts as an important bottleneck that limits the improvement of processor performance. To address this limitation, hardware prefetching is an important complement to multi-level cache technology. Strid data prefetcher and page data prefetcher are the two most commonly used hardware data prefetching techniques with different characteristics and performance effects. By combining the stride and page prefetcher, a design that fuses the stride and page prefetcher is proposed, which improves the coverage and processing accuracy in the case of limited prefetching capacity. In addition, different prefetch designs are implemented on FPGA platforms. Actual test programs from SPEC2006 were tested by loading Uboot and OS. The results show that the miss rate of L1D and L2 caches is improved by 22.39% and 33.70% respectively, better than the single stride prefetcher or page prefetcher.