Implementation and Performance Evaluation of Various Reversible Vedic Multiplier Architectures for Reversible Digital Filters

Abstract

Reversible logic has emerged as an alternative technology to the traditional logic due to the narrowed scope for continued transistor scaling which is considered to be the primary factor driving the semiconductor industry, by the exponential growth of leakage current and other short channel effects that degrades the performance of the device. Reversible design eliminates information loss and thus reduces the power dissipation. Vedic multiplier belongs to the class of fast multipliers that incredibly improves the overall system efficiency. Thus, a reversible Vedic multiplier effectively combines both the low-power advantage of reversible design and the high-speed advantage of a Vedic multiplier. This paper presents the implementation of various architectures of reversible Vedic multiplier units based on Urdhva Tiryagbhyam Sutra and comparison of its performance in terms of the cost metrics like gate count, auxiliary inputs, garbage output and quantum cost along with factors like the power consumption and area. We have implemented six different architectures of the reversible Vedic Multiplier and compared its performance. The design is implemented using Xilinx 14.7 ISE using Verilog HDL on Spartan 6 FPGA.