Abstract
This paper presents the preliminary results of various configuration schemes for onboard and off-board components using built-in Peripheral Component Interconnect (PCIe) interface of Intel Arria 10 FPGA. This is part of A Large Ion Collider Experiment-Common Readout Unit (ALICE-CRU) upgrade program that will configure CRU itself as well as associated on-detector ASICs of most of the sub-detectors prior data acquisition. In this paper, the different configuration schemes based on Inter-Integrated Circuit (I2C) and High-level Data Link Control (HDLC) protocol will be explained. The main motivation of this paper is to discuss the glue logics that have been developed during evaluation of those protocols. The result obtained during evaluation will also be presented.
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