Impedance Characteristics and Chip-Parasitics Extraction of High-Performance VCSELs

Abstract

In order to analyze the physical limitations and develop highly performing vertical-cavity surface-emitting lasers (VCSELs), it is essential to have an in-depth understanding of their intrinsic laser dynamics. However, the high-speed performance of such devices is impaired by its extrinsic dynamic response associated with the VCSEL chip parasitics. A first-order low-pass filter transfer function is traditionally used to de-embed this parasitic part from the total VCSEL modulation response. However, this oversimplification results in large discrepancies between the modeled and the measured parasitic-network response, leading to a high level of uncertainty in the extracted circuit component values. Further, intrinsic parameters can only be gained to a frequency range, where the parasitic response is flat and de-embedding not critical. In this work, a novel advanced parasitic-network model that well describes the extrinsic behavior of high-performance VCSELs is reported. In this model, besides the standard parasitic elements, the contact-pads with their capacitance with frequency-dependent dielectric losses and their inductance are considered. Moreover, for this advanced parasitic-network model to reveal its full potential, a rigorous fitting methodology is also described in this work. This proposed novel model, along with the strict fitting procedure, accurately replicate the delicate $S_{{11}}$ data even at high-frequencies and enable the extraction of highly reliable circuit component values. This model can not only describe and model the parastitic chip response accurately but can be implemented to optimize the chip design, hence improving the parasitic bandwidth limitations in high-speed VCSELs.