Impacts of Surface Roughness Reduction in (110) Si Substrates Fabricated by High-Temperature Annealing on Electron Mobility in n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors on (110) Si

Abstract

The effects of high-temperature Ar/H2 annealing on (110) Si, which is known to provide flat (110) Si surfaces, have been studied from the viewpoint of metal–oxide–semiconductor (MOS) interface roughness and inversion-layer electron mobility limited by surface roughness scattering in (110) Si n-channel metal–oxide–semiconductor field-effect transistors (n-MOSFETs). It has been confirmed by quantitative transmission electron microscope (TEM) analysis that the reduction in the surface roughness on (110) Si is still maintained after gate oxidation with gate oxide thickness (Tox) of 6.9 nm. The mobility measurement of (110) Si n-MOSFETs fabricated using Si wafers with high-temperature Ar/H2 annealing has revealed that the high-temperature annealing increases the electron mobility of (110) Si MOSFETs at 10 K by 14 and 5.7% for Tox values of 6.9 and 8.9 nm, respectively, and increases the electron mobility at 300 K by 2.5 and 0.72% for Tox values of 6.9 and 8.9 nm, respectively. The Tox dependence of the enhancement factor might be attributable to the increase in MOS interface roughness with increasing Tox. It has also been observed that the mobility enhancement factor is slightly dependent on the channel direction. The mobility increase has been observed to be greater along <111> than along <112>.