Impacts of Floating Poly on Electrostatic Discharge Protection of Power-Managed High-Voltage Laterally Diffused Metal Oxide Semiconductor Components

Abstract

This study used a TSMC 0.18 µm 50 V process to build a high-voltage n-LDMOS structure. In the reference device, the number of floating poly (poly-2) turns was 7, and the width and spacing of each turn was 1 µm. The experiment was realized in three steps, i.e., fixing the number of laps by occupying the width of the structure, adjusting the width of each turn, and adjusting the distance between turns. The first step was fixed to occupy the width of the structure chart to adjust the number of turns. The number of turns increased from 7 to 9 and then decreased to 5 and 3 turns. The reduction in the number of turns resulted in a greater reduction in maximum electric field and an increase in breakdown voltage. A comparison of the 3-turn set with the reference set showed a 42% reduction in maximum electric field, from 4.17 × 103 to 2.46 × 103 (V/cm), and an increase in breakdown voltage (VBK) from 30.2 V to 35.84 V. The second step was to adjust the width of each turn from 1 to 1.4, 1.2, 0.8, and 0.6 µm. This increase in width reduced the maximum electric field, resulting in a greater increase in VBK. When the width was increased to 1.4 µm, the maximum field decreased from 1.95 × 103 V/cm to 1.4 × 103 V/cm and the VBK increased from 30.2 V to 85.6 V, an increase of 183%. The third step was to adjust the per-turn spacing of the reference group from 1 to 1.4, 1.2, 0.8, and 0.6 µm. When the spacing was reduced to 0.6 µm, the maximum electric field decreased by 33% from 1.95 × 103 to 1.32 × 103 V/cm and the VBK increased by 345% from 30.2 to 134.4 V.