Impact quantification of the dummy metal fills on nanometer VLSI designs for DFM

Abstract

Dummy metal fills can cause systematic variations in capacitance and the impact on the parametric yields should be quantified rigorously. A new set of experimental nanometer circuit structures with close-to-reality dummy metal fills are designed and simulated using 3-D electromagnetic field simulations and SPICE to quantify the impacts on the capacitance, the timing, and the crosstalk noise more realistically for design for manufacturability (DFM). With the proposed set of test structures scaled down for the upcoming advanced technology nodes, the foundries and the designers can incorporate the parasitic impacts by dummy metal fills as part of the systematic variation for LPE and SSTA tools. From our detailed analyses, the impacts are growing from 180nm to 90nm and are likely to become more prominent in 65nm and 45nm designs.