Abstract

Monolithic three-dimensional (M3D) integration has the potential to achieve significantly higher device density compared to 3D integration based on through-silicon vias. We analyze defects that arise due to voids created during the wafer-bonding step in M3D integration. We quantify the impact of these defects on the threshold voltage of a top-layer transistor in an M3D integrated circuit. We also show that wafer-bonding defects can lead to a change in the resistance of inter-layer vias (ILVs), and in some cases, lead to an open in an ILV or a short between two ILVs. We then analyze the impact of these defects on path delays. Our results show that the timing characteristics of an M3D IC can be significantly altered due to the presence of wafer-bonding defects.

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