Abstract
Stochastic device degradation — due to individual oxide defects — like Random Telegraph Noise (RTN) and Bias Temperature Instability (BTI) causes a threshold voltage drift of transistors resulting in decreased SRAM yield and performance. BTI and RTN has been shown to follow an defect-centric behavior, which can be bimodal in nature for heterogeneous gate oxide stacks. Consequently the tail of the distribution can significantly deviate from a Gaussian distribution. In this paper we combine statistical silicon extracted from large transistor arrays (32k) designed and fabricated in an advanced 20nm High-k/Metal Gate process, with current state-of-the-art statistical assessment techniques in order to acquire a realistic impact of BTI degradation on the yield and performance of 6T SRAM cells.
Published Version
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