Abstract
Thick epitaxial (3-15 microns) GaN power switching devices are known to contain a high density of crystal defects, and especially threading dislocations in the epitaxial layer. The impact of these defects on device performance and reliability is a topic of ongoing research. This paper presents state-of-the-art methods for analyzing threading dislocation density, growth, and quantification of their impact on leakage current, blocking voltage, and peak E field. The effects of substrate type, epitaxial thickness, and processing techniques on dislocation density have been investigated to provide a roadmap for design and performance optimization of switching two terminal devices. Experimental and simulated data are used in conjunction to model dislocation impact on electrical performance characteristics and to identify techniques to minimize defect density.
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