Impact of thermal through silicon via (TTSV) on the temperature profile of multi-layer 3-D device stack

Abstract

IC performance is now predominantly governed by interconnects delay due to smaller wire cross-section, wire pitch and longer lines that traverse across larger chips. These increase the resistance and capacitance hence signal latency of these lines. Material solutions such as Cu/low-kappa is no longer able to reduce interconnects delay time as pitch is scaled down further. 3-D ICs with multiple active Si layers is a promising technique to overcome this scaling barrier as it replaces long inter-block global wires with much shorter vertical inter-layer interconnects. Thermal dissipation in present 2-D circuits is known to significantly impact interconnect, performance and device reliability in a negative manner. This problem is expected to be exacerbated further in 3-D ICs as power generated by every silicon layers must now be dissipated through a smaller 3-D chip foot print. This results in a sharp increase in the power density and is a potential show-stopper to 3-D ICs if left unmanaged. In this work, a thorough thermal analysis of a vertically integrated stack consists of three IC layers bonded back to face (or facing up) is carried out using FEM tool. The focus of the present work is to investigate the effectiveness of thermal through silicon via (TTSV) in mitigating heat dissipation challenge at different layers.