Impact of the Gate and Insulator Geometrical Model on the Static Performance and Variability of Ultrascaled Silicon Nanowire FETs

Abstract

We investigate the effect of the geometrical model adopted for the gate electrode and for the insulator enveloping the access regions on the full-quantum simulation of ultrascaled nanowire FETs (NW-FETs). We compare the results obtained in the “minimal” geometry commonly used in simulations with those obtained in a more realistic one, able to fully account for the gate fringing effects. We evaluate the impact of the model geometry on the static performance of NW-FETs and discuss the interplay with the surface roughness and the random distribution of dopants. We find that the ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio evaluated in the minimal geometry can be remarkably underestimated in short devices, notably in the case of small length-to-width ratio. The roughness-induced current degradation and the sensitivity to the surface roughness variability can also suffer from nonnegligible underestimations when evaluated in this geometry. Finally, we point out that an inaccurate description of the device electrostatics is expected to result in an overestimation of the sensitivity to the doping-induced variability.