Abstract
There is no doubt that the CMOS technology scaling affects significantly the performance of the one-transistor one capacitor dynamic-random access memories (1T-1C DRAMs). In this paper, the effect of CMOS technology scaling and the change of the fabrication techniques of the access transistor and the cell-storage capacitor on the performance of DRAMs are investigated and discussed qualitatively. The metrics that are taken as the criteria for evaluating the performance of the DRAM are the chip area, the power consumption, the cycle time, and the sense margin. The simulation results ascertain this impact.
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