Abstract
With the concept of groove gate and implementing the idea of silicon on insulator (SOI), a new analytical model is developed for the rectangular recessed channel silicon on insulator (RRC-SOI) metal oxide semiconductor field effect transistor (MOSFET). This analytical model is formulated using 2D Poisson's equation and develops a compact equation for threshold voltage using minimum surface potential. This paper analyses the effect of negative junction depth (NJD) on device parameters, such as minimum surface potential, threshold voltage, sub-threshold slope (SS), and drain induced barrier lowering (DIBL). The impact of oxide thickness variation on the above parameters has also been evaluated. Further, the linearity performance in terms of figure of merits (FOM) and device parameters like drain current and trans-conductance of the proposed model is compared with the simulated results of rectangular recessed channel (RRC) MOSFET. The validity of the proposed model has been verified with simulation results performed on Sentaurus TCAD device simulator.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
