Abstract
The impact of interface charges under the gate spacer on FDSOI devices integrated in low temperature process are explored. A great number of traps (~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> /cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) are identified on the interface between the spacer oxide and the silicon film using Terman's method for interface states characterization. Thanks to electrical characterization and TCAD simulations, it is shown that the trapped charges induce the formation of a depleted region in the vicinities of the spacer. Moreover, a strong degradation of performances on underlap channels is observed. The spacer charges influence on reliability measurements is finally explored.
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