Impact of Source-to-Gate and Drain-to-Gate Overlap Lengths on Performance of Inverted Staggered a-IGZO TFTs With an Etch Stopper

Abstract

We report a comprehensive study on the impact of source-to-gate ( ${L}_{S}$ ) and drain-to-gate ( ${L}_{D}$ ) overlap lengths on the performance of amorphous indium–gallium–zinc–oxide (a-IGZO) thin-film transistors (TFTs) employing the inverted staggered structure with an etch stopper (ES). Although drain current ( ${I}_{D}$ ) is found to marginally decrease with increasing ${L}_{S}$ , it is found to considerably increase with ${L}_{D}$ . With the help of technology computer-aided design (TCAD) simulations, the increase in ${I}_{D}$ with ${L}_{D}$ is attributed to backchannel formation in the region beneath the drain, while the decrease in ${I}_{D}$ with increasing ${L}_{S}$ is attributed to the depletion of carriers from the backchannel in the region beneath the source. In addition, the threshold voltage ( ${V}_{TH}$ ) shifts negatively with increasing ${L}_{D}$ and drain voltage ( ${V}_{D}$ ). All these effects are more pronounced in short channel TFTs than long channel TFTs, which could be the origin of the anomalous dependence of ${V}_{TH}$ of the ES-type a-IGZO TFTs on channel length.